Plate defect mitigation techniques

An electronic memory apparatus, comprising:

• a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
• a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
• a first cell plate included in the first cell plate group;
• and
• a second cell plate adjacent to the first cell plate and included in the second cell plate group, wherein the first cell plate and the second cell plate are in electronic communication via a short between the first cell plate and the second cell plate.

An electronic memory apparatus, comprising:

• a first cell plate included in a first cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
• a second cell plate included in a second cell plate group comprising a plurality of sequential cell plates that are immediately adjacent;
• a first digit line in electronic communication with the first cell plate and a first sense amp via a first transistor;
• a second digit line in electronic communication with the second cell plate and a second sense amp via a second transistor;
• and
• a controller in electronic communication with the first sense amp and the second sense amp, wherein the controller is operable to:
• select the first cell plate and the second cell plate based at least in part on a short between the first cell plate and the second cell plate;
• and
• read information from at least one of the first sense amp and the second sense amp based at least in part on the selection.