US 2017/0365355 A1Published application

Memory controller for selecting read clock signal

AssigneeNXP USA, Inc.

InventorsSHAOHU WANG, Bin Li

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Abstract

A memory controller includes a clock delay generator, a set of flip-flops, and a control circuit, and is connected to a processor and a memory. The clock delay generator receives a clock signal from the processor, delays the clock signal by a set of delay time intervals, and generates a set of delayed clock signals. The flip-flops receive a test pattern and read data from the memory, sample the test pattern and the read data based on the delayed clock signals, and generate a set of sampled test patterns and a set of sampled read data. The control circuit identifies a sampled test pattern that is equal to the test pattern and the corresponding delayed clock signal as a read clock signal, and outputs the sampled read data that corresponds to the (delayed) read clock signal.

Claims17

Dependent claims

A memory controller for processing a read transaction request, wherein the memory controller is connected to a processor for receiving the read transaction request and a clock signal and a memory for receiving read data corresponding to the read transaction request, the memory controller comprising:

a clock delay generator connected to the processor, wherein the clock delay generator receives the clock signal and generates a set of delayed clock signals using a set of delay time intervals;
a set of flip-flops that receives a test pattern, wherein the set of flip-flops is connected to the clock delay generator and the memory for receiving the set of delayed clock signals and the read data, respectively, and wherein the set of flip-flops samples the test pattern and the read data using each of the delayed clock signals of the set of delayed clock signals, and generates a set of sampled test patterns corresponding to the set of delayed clock signals and a set of sampled read data corresponding to the set of delayed clock signals;
and
a control circuit connected to the set of flip-flops for receiving the set of sampled test patterns and the set of sampled read data, and connected to the clock delay generator for receiving the set of delayed clock signals, wherein the control circuit compares each of the sampled test patterns of the set of sampled test patterns with the test pattern, selects a one of the delayed clock signals of the set of delayed clock signals as a read clock signal based on the comparison of the test pattern and the set of sampled test patterns, and outputs to the processor the sampled read data of the set of sampled read data that corresponds to the read clock signal, wherein the control circuit selects the one of the delayed clock signals as the read clock signal when a corresponding sampled test pattern is equal to the test pattern.

1 more element

An integrated circuit (IC), comprising:

a processor that generates a read transaction request and a clock signal;
a memory that stores read data and a test pattern;
and
a memory controller connected between the processor and the memory, for receiving the read data and the test pattern from the memory, and the read transaction request and the clock signal from the processor, wherein the memory controller generates a read clock signal for sampling the read data, and outputs sampled read data, wherein the memory controller comprises:
a clock delay generator connected to the processor for receiving the clock signal, delaying the clock signal by a set of delay time intervals, and generating a set of delayed clock signals based on the set of delay time intervals;
a set of flip-flops that receives the test pattern and the read data from the memory, and the set of delayed clock signals from the clock delay generator, samples the test pattern and the read data using each of the delayed clock signals of the set of delayed clock signals, and generates a set of sampled test patterns corresponding to the set of delayed clock signals, and a set of sampled read data corresponding to the set of delayed clock signals;
and
a control circuit connected to the set of flip-flops for receiving the set of sampled test patterns and the set of sampled read data, and connected to the clock delay generator for receiving the set of delayed clock signals, wherein the control circuit compares each of the sampled test patterns of the set of sampled test patterns with the test pattern, and selects a one of the delayed clock signals of the set of delayed clock signals as a read clock signal based on the comparison of the test pattern and the set of sampled test patterns, and outputs the sampled read data of the set of sampled read data that corresponds to the read clock signal, wherein the control circuit determines the one delayed clock signal as the read clock signal when a corresponding sampled test pattern is equal to the test pattern.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/364,274Filed 30 Nov 2016
Priority: CN 201610450837.521 Jun 2016
Published: 21 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 29/36
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: data generation devices, e.g. data inverters
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…