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US 2017/0365348 A1Published application
Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsYoshihiko KAMATA, Yoko DEGUCHI, Takuyo KODAMA, Tsukasa KOBAYASHI, Mario SAKO, Kosuke YANAGIDAIRA
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.
Claims20
A semiconductor memory device, comprising:
- a memory cell;
- a bit line connected to the memory cell;
- and
- a sense amplifier connected to the memory cell through the bit line, wherein the sense amplifier includes
- a sense node connected to the bit line,
- a first capacitive element connected to the sense node, and
- a static latch circuit connected to the sense node and retains data of the sense node.
4 more elements
A semiconductor memory device, comprising:
- first and second memory cells;
- first and second bit lines connected to the first and second memory cells, respectively;
- first and second sense amplifiers connected to the first and second bit lines, respectively;
- and
- a first circuit that connects the first and second sense amplifiers,
- wherein the first sense amplifier includes,
- a first sense node connected to the first bit line,
- a first capacitive element connected to the first sense node, and
- a first static latch circuit connected to the first sense node and retains data of the first sense node, and
- wherein the second sense amplifier includes,
- a second sense node connected to the second bit line,
- a second capacitive element connected to the second sense node, and
- a second static latch circuit connected to the second sense node and retains data of the second sense node.
10 more elements
A semiconductor memory device, comprising:
- a memory cell;
- a bit line connected to the memory cell;
- and
- a sense amplifier connected to the memory cell through the bit line, the sense amplifier including a sense node connected to the bit line, a first capacitive element connected to the sense node, and a latch circuit, wherein
- the latch circuit includes a first inverter comprising a first PMOS transistor and a first NMOS transistor which are connected in series to each other, and a second inverter comprising a second PMOS transistor and a second NMOS transistor which are connected in series to each other, and
- the sense node is connected to an input of the first inverter and an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter.
3 more elements
Dependencies are inferred from the claim text.