Semiconductor device

A semiconductor device comprising:

• a memory cell array;
• a sense amplifier electrically connected to memory cells of the memory cell array and including a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate;
• and
• a voltage generation circuit configured to supply voltages to the sense amplifier, and
• wherein one of the voltages supplied by the voltage generation circuit is a bias voltage for adjusting a substrate bias of the first transistor to cause a threshold voltage of the first transistor to be substantially constant across different temperatures, and
• wherein the voltage generation circuit includes
• a first circuit configured to generate a first voltage based on a first current,
• a second circuit that includes a second transistor of the first conductivity type having a third terminal, a fourth terminal, and a second gate, the second circuit configured to generate a second voltage based on a voltage difference between the third terminal and the fourth terminal, and
• a third circuit configured to compare the first voltage and the second voltage, and generate the bias voltage for adjusting the substrate bias of the first and second transistors, based on the comparison result, the third circuit including an amplification circuit and a clamp circuit, the amplification circuit generating an interim voltage based on the comparison result and the clamp circuit generating the third voltage based on the interim voltage.

A semiconductor device comprising:

• a first circuit configured to generate a first voltage based on a first current;
• a second circuit that includes a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate, the second circuit configured to generate a second voltage based on a voltage difference between the first terminal and the second terminal;
• and
• a third circuit configured to compare the first voltage and the second voltage, and generate a third voltage for adjusting a substrate bias of the first transistor, based on the comparison result,
• wherein the third circuit includes an amplification circuit and a clamp circuit, the amplification circuit generating an interim voltage based on the comparison result and the clamp circuit generating the third voltage based on the interim voltage.