High voltage architecture for non-volatile memory

A method comprising:

• applying a first high voltage signal (VPOS) to a common source line (CSL) and bit line (BL), each coupled to a non-volatile memory (NVM) cell during an erase operation;
• applying a second high voltage signal (VNEG) to a word line (WL) and to a substrate line (SPW), each coupled to the NVM cell during a program operation;
• and
• wherein:
• the first high voltage signal is above a highest voltage of a power supply;
• and
• the second high voltage signal is below a lowest voltage of a ground supply of the memory device.

A system, comprising:

• a plurality of non-volatile memory (NVM) cells in a sector, each NVM cell coupled to a common source line (CSL);
• a local bit line (BL) coupled to at least one NVM cell;
• a word line (WL) coupled to at least one NVM cell;
• and
• a sector select circuit, coupled to a column of NVM cells in the sector having at least one transistor disposed between the bit line and a common line (CL), the sector select circuit controlling a bit line voltage applied to the local bit line.

A method comprising:

• applying a first high voltage signal (VPOS) to a first word line (WLS) coupled to the NVM cell during a pre-programming operation;
• applying a second high voltage signal (VNEG) to a second word line (WL) and to a substrate line (SPW) coupled to the NVM cell;
• and
• applying a third high voltage signal (VNEG3) to a common source line (CSL) coupled to the NVM cell;
• wherein:
• the common source line is shared among NVM cells of a sector of NVM cells;
• and
• the first high voltage signal is above a highest voltage of a power supply.