US 2017/0365344 A1Published application

Methods of operating a memory during a programming operation

AssigneeMicron Technology, Inc.

InventorsYogesh Luthra, Kim-Fung Chan, Xiaojiang Guo

Life of this patent

Estimating the term…

Loading patent…

Abstract

Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.

Claims20

Dependent claims

A method of operating a memory, comprising:

increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage, wherein the first access line is coupled to a first plurality of memory cells comprising a target memory cell targeted for a programming operation and an unselected memory cell not targeted for the programming operation;
while increasing the voltage applied to the first access line from the first voltage to the second voltage:
electrically connecting a first semiconductor pillar, providing a channel region of the target memory cell, to a first data line;
and
applying the first voltage to a second access line, wherein the second access line is coupled to a second plurality of memory cells each not targeted for the programming operation, and wherein the first semiconductor pillar and the second semiconductor pillar each provide a channel region for a respective memory cell of the second plurality of memory cells;
after increasing the voltage applied to the first access line from the first voltage to the second voltage, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage;
and
while increasing the voltage applied to the first access line from the second voltage to the third voltage:
electrically connecting a first semiconductor pillar to the first data line;
electrically isolating a second semiconductor pillar, providing a channel region of the unselected memory cell, from a second data line;
and
increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.

9 more elements

A method of operating a memory, comprising:

increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage, wherein the first access line is coupled to a first plurality of memory cells comprising a target memory cell targeted for a programming operation and an unselected memory cell not targeted for the programming operation;
while increasing the voltage applied to the first access line from the first voltage to the second voltage:
electrically connecting a first semiconductor pillar, providing a channel region of the target memory cell, to a first data line;
electrically isolating the second semiconductor pillar, providing a channel region of the unselected memory cell, from a second data line;
electrically isolating the first semiconductor pillar and the second semiconductor pillar from a common source;
and
applying the first voltage to a second access line, wherein the second access line is coupled to a second plurality of memory cells each not targeted for the programming operation, and wherein the first semiconductor pillar and the second semiconductor pillar each provide a channel region for a respective memory cell of the second plurality of memory cells;
after increasing the voltage applied to the first access line from the first voltage to the second voltage, maintaining the voltage applied to the first access line at the second voltage for a period of time;
after maintaining the voltage applied to the first access line at the second voltage for the period of time, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage;
and
while increasing the voltage applied to the first access line from the second voltage to the third voltage:
electrically connecting a first semiconductor pillar to the first data line;
electrically isolating the second semiconductor pillar from the second data line;
and
increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage.

12 more elements

A method of operating a memory, comprising:

increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage, wherein the first access line is coupled to a first plurality of memory cells comprising a target memory cell targeted for a programming operation and an unselected memory cell not targeted for the programming operation;
while increasing the voltage applied to the first access line from the first voltage to the second voltage:
electrically connecting a first semiconductor pillar, providing a channel region of the target memory cell, to a first data line;
electrically connecting the second semiconductor pillar, providing a channel region of the unselected memory cell, to a second data line;
electrically isolating the first semiconductor pillar and the second semiconductor pillar from a common source;
and
applying the first voltage to a second access line, wherein the second access line is coupled to a second plurality of memory cells each not targeted for the programming operation, wherein the first semiconductor pillar and the second semiconductor pillar each provide a channel region for a respective memory cell of the second plurality of memory cells;
after increasing the voltage applied to the first access line from the first voltage to the second voltage, maintaining the voltage applied to the first access line at the second voltage for a period of time;
after maintaining the voltage applied to the first access line at the second voltage for the period of time, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage;
and
while increasing the voltage applied to the first access line from the second voltage to the third voltage:
electrically connecting a first semiconductor pillar to the first data line;
electrically isolating the second semiconductor pillar from the second data line;
and
increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/692,073Filed 31 Aug 2017
Priority: 3 May 2016
Published: 21 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
G11C 16/32
Auxiliary circuits, e.g. for writing into memory: timing circuits

Family

Application15/145,204Continuation · filed 3 May 2016
Application15/499,119Continuation · filed 27 Apr 2017
Application15/692,073Continuation
US 10,163,514 B2Related patent
US 9,666,282 B1Related patent
US 9,779,822 B1Related patent
US 9,805,801 B1Related patent
US 2017/0365344 A1This patent

From the US filing history. Foreign family members aren’t listed.