Memory as a programmable logic device

A method for operating a memory, the method comprising:

• programming a plurality of first series strings of memory cells of a first group of memory cells such that pairs of complementary memory cells of each first series string of the plurality of first series strings have complementary states to provide a respective first minterm for each first series string of the plurality of first series strings, wherein each respective first minterm comprises a plurality of first variables, and wherein each variable of the plurality of first variables of each respective first minterm is enabled responsive to a state of its respective memory cell;
• and
• programming a plurality of second series strings of memory cells of a second group of memory cells such that pairs of complementary memory cells of each second series string of the plurality of second series strings have complementary states to provide a respective second minterm, each respective second minterm comprising a respective first minterm of a corresponding first series string of memory cells of the plurality of first series strings of memory cells that is enabled responsive to the state of its respective memory cell, wherein each respective second minterm further comprises a plurality of second variables, and wherein each variable of the plurality of second variables of each respective second minterm is enabled responsive to a state of its respective memory cell.

A memory comprising:

• a plurality of memory cells configured in groups of memory cells, each group of memory cells configured in a NAND architecture comprising a plurality of series strings of memory cells;
• wherein a first group of memory cells is configured to provide a first logical function comprising a first plurality of minterms, wherein each minterm of the first plurality of minterms comprises a plurality of variables, and wherein each variable of that plurality of variables is enabled responsive to a state of an associated, respective memory cell;
• wherein each series string of memory cells of the respective plurality of series strings of memory cells of the first group of memory cells is configured to receive a same set of control gate signals to the memory cells of that series string of memory cells;
• wherein each series string of memory cells of the respective plurality of series strings of memory cells of the first group of memory cells is selectively connected to a particular data line of the memory;
• wherein a second group of memory cells is configured to provide a second logical function comprising a second plurality of minterms, wherein each minterm of the second plurality of minterms comprises a plurality of variables, and wherein each variable of that plurality of variables is enabled responsive to a state of an associated, respective memory cell;
• wherein each series string of memory cells of the respective plurality of series strings of memory cells of the second group of memory cells is configured to receive a same set of control gate signals to only a portion of the memory cells of that series string of memory cells;
• wherein each series string of memory cells of the respective plurality of series strings of memory cells of the second group of memory cells is selectively connected to a different data line of the memory;
• and
• wherein a particular minterm of a particular series string of memory cells of the respective plurality of series strings of memory cells of the second group of memory cells comprises the first logical function from the particular data line, the first logical function enabled responsive to a state of an associated, respective memory cell.