Memory Devices Including Buffer Memory and Memory Modules Including the Same

A memory module comprising:

• a first memory device;
• and
• a second memory device having a different operation speed or different capacity from the first memory device,
• wherein the first memory device comprises:
• a memory cell array including a plurality of memory cells;
• a first bit line sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines and configured to amplify a signal of the plurality of bit lines;
• a second bit line sense amplifier circuit disposed adjacent to the first bit line sense amplifier circuit and not connected to any of the plurality of bit lines;
• and
• a row decoder configured to select a plurality of word lines connected to the plurality of memory cells and a sub word line connected to the second bit line sense amplifier circuit.

A memory module comprising:

• first and second ultra-capacitive memory devices;
• first and second memory devices configured to provide a cache for the first and second ultra-capacitive memory devices;
• first and second data buffers configured to transmit inputted data inputted to the first and second memory devices or to the first and second ultra-capacitive memory devices;
• and
• a register clock driver configured to determine whether to drive the first and second ultra-capacitive memory devices or the first and second memory devices.