Memory device with improved latency and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSOO-HO CHA, CHANKYUNG KIM, SUNGCHUL PARK, KWANGCHOL CHOE
Life of this patent
Estimating the term…
Abstract
Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.
Claims21
A memory device comprising:
- a first memory cell connected to a word line and a first bit line;
- a second memory cell connected to the word line and a second bit line;
- and
- a row decoder configured to select the word line,
- wherein a first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell, and
- wherein the first hit line is selected based on a time point when the first memory cell is activated.
A memory device comprising:
- a first memory block comprising a first memory cell connected to a word line and a first bit line;
- a second memory block comprising a second memory cell connected to the word line and a second bit line;
- and
- a row decoder configured to select the word line,
- wherein a first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell, and
- wherein the first bit line is selected based on a time point when the first memory cell is activated.
A method of operating a memory device that comprises a first memory cell and a second memory cell connected to a row decoder through a word line and connected to a column decoder through a first bit line and a second bit line, the method comprising;
- activating the first memory cell and the second memory cell connected to the word line selected by the row decoder;
- and
- selecting the first bit line and the second bit line based on a time point when the first memory cell is activated,
- wherein a first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell.
21-23. (canceled)
Dependencies are inferred from the claim text.