Comparison operations in memory

A system, comprising:

• a first group of memory cells coupled to a first access line and configured to store a plurality of elements;
• a second group of memory cells coupled to a second access line and configured to store a plurality of elements;
• wherein:
• the elements stored in the first group and the second group each include a first element and a second element having different bit lengths;
• and
• the first element stored in the first group has a bit length equal to a bit length of the first element stored in the second group and the second element stored in the first group has a bit length equal to a bit length of the second element stored in the second group;
• and
• a controller configured to cause:
• a first element pair to be compared by controlling sensing circuitry to perform a number of operations, the first element pair comprising the first element stored in the first group and the first element stored in the second group;
• and
• a second element pair to be compared in parallel with the first element pair, the second element pair comprising the second element stored in the first group and the second element stored in the second group.

A method for operating a system, the method comprising:

• receiving, at a controller coupled to a memory device, a command to perform comparison operations in a memory;
• performing a plurality of comparison operations by:
• storing a plurality of first elements in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array;
• and
• storing a plurality of second elements in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array;
• wherein corresponding element pairs of the plurality of first elements and the plurality of second elements have a same bit length, each element pair comprising a first element stored in the first group and a second element stored in the second group;
• wherein at least one of the plurality of first elements comprises a bit length different than a bit length of at least one other of the plurality of first elements;
• and
• comparing the plurality of first elements to the plurality of second elements.

A system, comprising:

• a first group of memory cells coupled to a first access line and to a number of sense lines and configured to store a plurality of first elements;
• a second group of memory cells coupled to a second access line and to the number of sense lines and configured to store a plurality of second elements;
• a third group of memory cells coupled to a third access line and to the number of sense lines and configured to store results of a plurality of comparison operations performed on the plurality of first elements and the plurality of second elements;
• and
• a controller configured to control sensing circuitry to perform the plurality of comparison operations and store the results of the plurality of comparison operations in the third group of memory cells.