Memory device including memory cell for generating reference voltage

A memory device comprising:

• a reference voltage generation circuit comprising a first memory cell coupled between a first wordline and a first bitline and a second memory cell coupled between the first wordline and a second bitline;
• a third memory cell connected to the first wordline and a third bitline;
• and
• a bitline sense amplifier connected to the third bitline,
• wherein the reference voltage generation circuit generates a first reference voltage by performing charge sharing between the first memory cell and the first bitline and generates a second reference voltage by performing charge sharing between the second memory cell and the second bitline.

A memory device comprising:

• a controller configured to generate a first control signal and a second control signal;
• a first memory cell connected to a first wordline and a first bitline;
• a second memory cell connected to the first wordline and a second bitline;
• a third memory cell connected to the first wordline and a third bitline;
• a bitline sense amplifier connected to the third bitline;
• a first switch circuit configured to connect the first bitline to a first reference voltage line and the second bitline to a second reference voltage line in response to the first control signal;
• and
• a second switch circuit configured to connect one of the first and second reference voltage lines to the bitline sense amplifier in response to the second control signal.