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US 2017/0365302 A1Published application
Latching current sensing amplifier for memory array
AssigneeGlobalfoundries Inc.
InventorsDarren L. ANAND, John A. FIFIELD, Eric D. HUNT-SCHROEDER, Mark D. JACUNSKI
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Abstract
A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
Claims15
A circuit, comprising:
- a first pair of p-type transistors (PFETs) connected in series;
- a second pair of PFETs connected in series;
- a first PFET of the first pair of PFETs and a second PFET of the second pair of PFETs are cross coupled by a common node;
- and
- a second PFET of the first pair of PFETs and a first PFET of the second pair of PFETs are cross coupled by the common node.
2 more elements
A method comprising:
- injecting a first pair of currents into a true bitline (BLT) and a complement bitline (BLC) connected to a storage cell, wherein the first pair of currents is self biased;
- drawing a second pair of currents out of the BLT and the BLC to provide gain and a voltage output;
- and
- once initial current sensing is complete, disconnecting the self-bias and latching transistors with a common node enabled by a latching signal to form a cross-coupled latch,
- wherein the sensing and latching is controlled by a single digital input, and signal margining is done by differential adjustment of the second pair of currents.
2 more elements
Dependencies are inferred from the claim text.