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US 2017/0365299 A1Published application
Apparatuses and methods for performing logical operations using sensing circuitry
AssigneeMicron Technology, Inc.
InventorsGlen E. Hush, Troy A. Manning
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.
Claims21
-20. (canceled)
A system, comprising:
- a memory device comprising an array of memory cells coupled to sensing circuitry;
- and
- control circuitry configured to operate the array and sensing circuitry to perform logical operations without enabling column decode lines;
- wherein the sensing circuitry comprises:
- a sense amplifier coupled to a pair of complementary sense lines corresponding to a column of the array;
- and
- a compute component coupled to the sense amplifier and comprising a dynamic latch;
- and
- wherein the control circuitry is configured to:
- activate a selected logical operation control signal corresponding to a selected logical operation;
- wherein activation of the selected logical operation control signal causes a result of the selected logical operation between a data value residing in the dynamic latch and a data value residing in a latch of the sense amplifier to be stored initially in the latch of the sense amplifier by overwriting the data value residing in the latch of the sense amplifier or leaving the data value residing in the latch of the sense amplifier unchanged depending on the selected logical operation.
8 more elements
A method, comprising:
- loading a first data value to a dynamic latch of a compute component coupled to an array of memory cells via a pair of complementary sense lines, wherein loading the first data value includes activating a first control signal associated with a load transistor of the compute component;
- storing a second data value in a latch of a sense amplifier coupled to the compute component via the pair of complementary sense lines;
- performing a selected logical operation using the first data value and the second data value as inputs to the selected logical operation, wherein performing the selected logical operation includes activating a second control signal associated with the selected logical operation;
- and
- wherein activating the second control signal causes a result of the selected logical operation to be stored initially in the latch of the sense amplifier by overwriting the second data value residing in the latch of the sense amplifier or leaving the second data value residing in the latch of the sense amplifier unchanged depending on the selected logical operation.
2 more elements
A system, comprising:
- a memory device comprising:
- an array comprising a plurality of complementary sense line pairs corresponding to respective columns of memory cells;
- sensing circuitry comprising a plurality of sense amplifier and compute component pairs corresponding to respective columns;
- and
- control circuitry configured to operate the array and sensing circuitry to perform a selected logical operation, in parallel, on a per column basis with the selected logical operation comprising a logical operation between a data value residing in a latch of the sense amplifier and a data value residing in a latch of the compute component of the respective sense amplifier and compute component pairs;
- wherein performing the selected logical operation comprises activating a selected logical operation control signal corresponding to the selected logical operation;
- and
- wherein activation of the selected logical operation control signal causes results of the selected logical operation to be stored initially in the latches of the respective sense amplifiers by overwriting the data values residing in the latches of the respective sense amplifiers or leaving the data values residing in the latches of the sense amplifiers unchanged depending on the selected logical operation.
5 more elements
Dependencies are inferred from the claim text.