Back to results
US 2017/0365220 A1Published application
Gate driving circuit and display panel including the same
AssigneeInnolux Corporation
InventorsSheng-Feng HUANG, Chien-Feng SHIH
Life of this patent
Estimating the term…
Abstract
A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.
Claims20
A gate driving circuit, comprising:
- at least one shift unit receiving a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal;
- and
- at least one switch unit connected to the shift unit and outputting a third clock signal based on the enable output signal.
A gate driving circuit, comprising:
- a first shift unit having a start input, a first clock input and a second clock input to receive a start input signal, a first clock input signal and a second clock input signal, respectively, and generating a first enable output signal;
- a second shift unit having a start input, a first clock input and a second clock input to receive the first enable output signal, the second clock input signal and the first clock input signal, respectively, and generating a second enable output signal;
- an inverting unit connected to the first shift unit and receiving the first enable output signal to generate an inverted first enable output signal;
- and
- a switch unit connected to the inverting unit and the second shift unit, the switching unit receiving a fourth clock signal and a fifth clock signal and outputting a sixth clock signal based on the inverted first enable output signal and the second enable output signal.
2 more elements
A display panel comprising:
- a gate driving circuit, comprising:
- a first shift unit having a start input, a first clock input and a second clock input to receive a start input signal, a first clock input signal and a second clock input signal, respectively, and generating a first enable output signal;
- a second shift unit having a start input, a first clock input and a second clock input to receive the first enable output signal, the second clock input signal and the first clock input signal, respectively, and generating a second enable output signal;
- an inverting unit connected to the first shift unit to receive the first enable output signal and generating an inverted first enable output signal;
- and
- a switch unit connected to the inverting unit and the second shift unit and receiving a fourth clock signal and a fifth clock signal to output a sixth clock signal based on the inverted first enable output signal and the second enable output signal;
- and
- a driving circuit comprising:
- a ninth transistor having a first end, a second end and a third end,
- a tenth transistor having a first end, a second end and a third end,
- a eleventh transistor having a first end, a second end and a third end, and
- a storage capacitor having an end and another end;
- wherein the first end of the ninth transistor is connected to a voltage, the second end of the ninth transistor is connected to the end of the storage capacitor, the second end of the eleventh transistor, and the third end of the ninth transistor is connected to the other end of the storage capacitor and the second end of the tenth transistor,
- wherein the first end of the tenth transistor is connected to a data line, and the third end of the tenth transistor is connected to the gate driving circuit, and
- wherein the third end of the eleventh transistor is connected to the gate driving circuit, and the first end of the eleventh transistor is connected to a compensating signal line.
12 more elements
Dependencies are inferred from the claim text.