Reliability enhancement methods for physically unclonable function bitstring generation
AssigneeStc.Unm
InventorJames PLUSQUELLIC
Life of this patent
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Abstract
A Hardware-Embedded Delay Physical Unclonable Function (“HELP PUF”) leverages entropy by monitoring path stability and measuring path delays from core logic macros. Reliability and security enhancing techniques for the HELP PUF reduce bit flip errors during regeneration of the bitstring across environmental variations and improve cryptographic strength along with the corresponding difficulty of carrying out model building attacks. A voltage-based enrollment process screens unstable paths on normally synthesized (glitchy) functional units and reduces bit flip errors by carrying out enrollment at multiple supply voltages controlled using on-chip voltage regulators.
Claims22
A reliability enhancement method to reduce the number of bit flips during physically unclonable function bitstring generation comprising the step of:
- measuring a path delay value of each launch capture interval of a plurality of intervals;
- calculating a difference value between two randomly selected path delay values;
- defining the difference value as a ‘0’ bit when the difference value is positive and a ‘1’ bit when the difference value is negative;
- generating a family of bitstrings based on the defining step, each bitstring generated at two or more supply voltage regulators;
- and
- eliminating the family of bitstrings by identifying inconsistencies in one or more bit positions of each bitstring generated at the two or more supply voltage regulators.
An enrollment method for bitstring generation by an integrated circuit, comprising the step of:
- (a) measuring a plurality of launch-capture interval path timing values for a physically unclonable function;
- (b) selecting randomly two path timing values of the physically unclonable function;
- (c) calculating a difference value between the two path timing values;
- (d) assigning a ‘0’ bit when the difference value is positive and a ‘1’ bit when the difference value is negative;
- (e) performing steps (a)-(d) at two or more supply voltage regulators to obtain two or more bitstrings;
- and
- (f) identifying inconsistencies in the two or more bit strings;
- and
- (g) removing the inconsistent bitstrings to reduce the number of bit flips.
Dependencies are inferred from the claim text.