US 2017/0364620 A1 · Verification of Untimed Nets

Abstract

Integrated circuits (ICs) rely on static timing analysis during their design to ensure that they will operate at desired frequencies. Delays between sequential elements (e.g., latches and flip-flops) are constrained to meet target clock periods. Certain signals, however, such as untimed nets may be excluded from timing constraints if the circuit function does not require these nets to switch and propagate to sequential elements within the clock period. However, a signal marked as “untimed” may have been mistakenly specified by the designer as an untimed net. To verify that an untimed net does not negatively impact the function of the design logic, the embodiments herein generate upstream and downstream event networks using shadow logic that corresponds to design logic upstream and downstream of the untimed net. A metastability network coupled to these networks is used to model nondeterminism and metastability resulting from transitions or potential glitches on the untimed net.

Claims20

Dependent claims

A method comprising:

receiving design logic comprising an untimed net, wherein the untimed net is indicated as being excluded from timing constraints;
generating, using one or more computer processors, an upstream event network using shadow logic, wherein the upstream event network comprises at least one untimed transition detector (UTD) corresponding to a first sequential element upstream from the untimed net in the design logic;
generating a downstream event network using shadow logic coupled to an output of the upstream event network, wherein the downstream event network comprises at least one metastability timer (MT) corresponding to a second sequential element downstream from the untimed net in the design logic;
and
generating a metastability network using shadow logic, wherein the metastability network is coupled to an output of the MT.

2 more elements

A computer program product for verifying function of a design logic comprising an untimed net, the computer program product comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to:
receive the design logic comprising the untimed net, wherein the untimed net is indicated as being excluded from timing constraints;
generate an upstream event network using shadow logic, wherein the upstream event network comprises at least one untimed transition detector (UTD) corresponding to a first sequential element upstream from the untimed net in the design logic;
generate a downstream event network using shadow logic coupled to an output of the upstream event network, wherein the downstream event network comprises at least one metastability timer (MT) corresponding to a second sequential element downstream from the untimed net in the design logic;
and
generate a metastability network using shadow logic, wherein the metastability network is coupled to an output of the MT.

3 more elements

Dependencies are inferred from the claim text.

Verification of Untimed Nets

Life of this patent

Verification of Untimed Nets

Life of this patent

Abstract

Claims20