Information processing apparatus, ising device, and information processing apparatus control method

An ising device comprising:

• a random signal generation circuit that outputs, a plurality of times, a selection signal for randomly selecting a first neuron whose output value is allowed to be updated from n neurons, wherein n is a natural number of 3 or more;
• d−1 arithmetic circuits that calculate, based on a plurality of weight values indicating strength of 2-body coupling to d-body coupling of two to d neurons including the first neuron selected from the n neurons based on the selection signal and n-bit output values of the n neurons, d−1 energy values indicating energies generated by the respective 2-body to d-body coupling or change amounts of the d−1 energy values, wherein d is a natural number not less than 3 and not more than n;
• an adder circuit that calculates a first sum by adding up the d−1 energy values or calculates a second sum by adding up the change amounts of the d−1 energy values and outputs the first sum or the second sum;
• a comparator circuit that determines and outputs a first output value of the first neuron, based on a first comparison result obtained by comparing a first value based on a sum of the first sum and a noise value with a threshold or based on a second comparison result obtained by comparing a third value with the threshold, the third value being based on a sum of a second value that indicates a sum of the energies generated by the respective 2-body to d-body coupling and that is updated based on the second sum and the noise value;
• an update circuit that outputs n-bit updated output values in which one bit has been updated based on the selection signal and the first output value;
• and
• a holding circuit that holds the n-bit updated output values and outputs the n-bit updated output values as the n-bit output values used by the arithmetic circuits.

An information processing apparatus control method comprising:

• preparing an ising device including:
• a random signal generation circuit that outputs, a plurality of times, a selection signal for randomly selecting a first neuron whose output value is allowed to be updated from n neurons, wherein n is a natural number of 3 or more,
• d−1 arithmetic circuits that calculate, based on a plurality of weight values indicating strength of 2-body coupling to d-body coupling of two to d neurons including the first neuron selected from the n neurons based on the selection signal and n-bit output values of the n neurons, d−1 energy values indicating energies generated by the respective 2-body to d-body coupling or change amounts of the d−1 energy values, wherein d is a natural number not less than 3 and not more than n,
• an adder circuit that calculates a first sum by adding up the d−1 energy values or calculates a second sum by adding up the change amounts of the d−1 energy values and outputs the first sum or the second sum,
• a comparator circuit that determines and outputs a first output value of the first neuron, based on a first comparison result obtained by comparing a first value based on a sum of the first sum and a noise value with a threshold or based on a second comparison result obtained by comparing a third value with the threshold, the third value being based on a sum of a second value that indicates a sum of the energies generated by the respective 2-body to d-body coupling and that is updated based on the second sum and the noise value,
• an update circuit that outputs n-bit updated output values in which one bit has been updated based on the selection signal and the first output value, and
• a holding circuit that holds the n-bit updated output values and outputs the n-bit updated output values as the n-bit output values used by the arithmetic circuits;
• causing a control device to set a plurality of weight values in the ising device;
• and
• causing the control device to control a noise width of the noise value.