Coherent controller

A method comprising:

• receiving, by a coherent controller, an instruction to provide data to a coherence bus, wherein at least one processor is coupled to the coherence bus;
• and
• responsive to receiving the instruction to provide data to the coherence bus:
• fetching, by the coherent controller, data from storage class memory;
• updating, by the coherent controller, a buffer to represent the data fetched from the storage class memory;
• and
• writing, by the coherent controller, at the coherence bus, an indication that data responsive to the instruction to provide data to the coherence bus is available at the buffer,
• wherein the at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the coherence bus after the coherent controller receives the instruction to provide data to the coherence bus and before the coherent controller writes the indication.

A non-transitory computer-readable storage medium encoded with instructions that, when executed, cause a controller to:

• receive an instruction to provide data to a bus, wherein at least one processor is coupled to the bus;
• and
• responsive to receiving the instruction to provide data to the bus:
• retrieve data from a storage class memory;
• update a buffer to represent the data retrieved from the storage class memory;
• and
• output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer,
• wherein the at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

A system comprising:

• means for receiving an instruction to provide data to a bus;
• means for retrieving data from storage class memory in response to receiving the instruction to provide data to the bus;
• means for updating a buffer to represent the data retrieved from the storage class memory in response to receiving the instruction to provide data to the bus;
• and
• means for outputting at the bus an indication that data responsive to the instruction to provide data to the bus is available at the buffer in response to receiving the instruction to provide data to the bus,
• wherein at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.