Techniques for implementing store instructions in a multi-slice processor architecture

A processor, comprising:

• an instruction cache;
• and
• an issue queue coupled to the instruction cache, wherein the issue queue is configured to:
• receive a store instruction, wherein the store instruction has an associated address generation (AGN) operation and an associated data operation;
• issue the AGN operation to AGN logic associated with a pipeline slice in response to all source operands for the AGN operation being ready, wherein the AGN logic is configured to generate an address for the store instruction;
• receive confirmation for the AGN operation, wherein the confirmation includes an indication of the pipeline slice that performed the AGN operation;
• and
• in response to receiving the confirmation and a source operand for the data operation being ready, issue the data operation to data logic associated with the pipeline slice indicated by the confirmation, wherein the data logic is configured to format data for the store instruction.

A data processing system, comprising:

• a data storage subsystem;
• and
• a processor coupled to the data storage subsystem, wherein the processor is configured to:
• receive a store instruction, wherein the store instruction has an associated address generation (AGN) operation and an associated data operation;
• issue the AGN operation to AGN logic associated with a pipeline slice in response to all source operands for the AGN operation being ready, wherein the AGN logic is configured to generate an address for the store instruction;
• receive confirmation for the AGN operation, wherein the confirmation includes an indication of the pipeline slice that performed the AGN operation;
• and
• in response to receiving the confirmation and a source operand for the data operation being ready, issue the data operation to data logic associated with the pipeline slice indicated by the confirmation, wherein the data logic is configured to format data for the store instruction.