Systems and Methods for Using Error Correction and Pipelining Techniques for an Access Triggered Computer Architecture

A system for improving performance of an access triggered architecture for a computer implemented application, the system comprising:

• a system memory element comprising a plurality of system memory locations;
• and
• at least one processor communicatively coupled to the system memory element, the at least one processor configured to:
• execute typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise:
• obtaining a dataset and an instruction set;
• and
• using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset;
• create a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time;
• and
• execute the typical operations according to the reduced execution time, using the pipeline.

A non-transitory, computer-readable medium containing instructions thereon, which, when executed by a processor, perform a method for improving performance of an access triggered architecture for a computer implemented application, the method comprising:

• executing typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise:
• obtaining a dataset and an instruction set wherein the instruction set comprises a plurality of instructions, including a current instruction consisting of a source pointer and a destination pointer;
• and
• using the instruction set to transmit the dataset to a functional block associated with an operation, by:
• retrieving the dataset from a first system memory location indicated by the source pointer;
• relocating the dataset to a second system memory location of the functional block, wherein the second system memory location is indicated by the destination pointer, to trigger execution of the operation associated with the second memory location, based on the instruction, wherein the functional block is configured to execute the operation when triggered, and wherein the functional block is triggered each time data is received at the second system memory location;
• performing the operation by the functional block at the second system memory location, using the dataset, to generate a result;
• and
• returning the generated result to the second system memory location, wherein the functional block performs the operation using the dataset to generate a revised dataset comprising the generated result;
• and
• creating a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time;
• and
• executing the typical operations according to the reduced execution time, using the pipeline.