Write buffer design for high-latency memories
AssigneeAdvanced Micro Devices, Inc.
InventorDavid A. Roberts
Life of this patent
Estimating the term…
Abstract
A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.
Claims19
A memory system, comprising:
- a write buffer;
- a main memory having a higher latency than the write buffer;
- a memory controller coupled with the main memory and with the write buffer, wherein the memory controller is configured to:
- in response to a write request indicating first data for storing at a write address in the main memory, add a new write entry in the write buffer, wherein the new write entry includes the write address and the first data,
- in response to the write request, update a pointer of a previous write entry in the write buffer to point to the new write entry, and
- in response to a write-back instruction, traverse a plurality of write entries stored in the write buffer including the previous write entry and the new write entry, and write into the main memory second data of the previous write entry and the first data of the new write entry.
A method, comprising:
- in response to a write request indicating first data for storing at a write address in a main memory,
- adding a new write entry in a write buffer, wherein the new write entry includes the write address and the first data, and
- updating a pointer of a previous write entry in the write buffer to point to the new write entry;
- and
- in response to a write-back instruction,
- traversing a plurality of write entries stored in the write buffer including the previous write entry and the new write entry, and
- writing into the main memory second data of the previous write entry and the first data of the new write entry, wherein the main memory has a higher latency than the write buffer.
A system, comprising:
- a write buffer;
- a main memory having a higher latency than the write buffer;
- a host processor comprising a memory controller, wherein the memory controller is coupled with the main memory and with the write buffer, and wherein the memory controller is configured to:
- for each write request of a plurality of write requests issued by the host processor, wherein the write request indicates first data for storing at a write address in the main memory,
- add a new write entry to a plurality of write entries in the write buffer, wherein the new write entry includes the write address and the first data, and
- update a next write pointer of a previous write entry in the write buffer to point to the new write entry, and
- in response to a write-back instruction issued by the processor, traverse the plurality of write entries in chronological order by, for each write entry of the plurality of write entries, copying data of the write entry to the main memory.
Dependencies are inferred from the claim text.