Active-Core-Based Performance Boost

A hardware system comprising:

• multiple cores, each core of the multiple cores configured to be powered up if active or powered down if inactive;
• and
• a power mode manager configured to enable activation of an independent power mode collection and an active-core-dependent power mode collection, the independent power mode collection including multiple independent power modes that are configured to be activated independently of a number of currently-active cores of the multiple cores, the active-core-dependent power mode collection including at least one dependent power mode that is configured to be activated conditioned on the number of currently-active cores of the multiple cores, the power mode manager including:
• means for providing a power-mode-triggering pathway to enable software to trigger an activation of an independent power mode of the independent power mode collection;
• and
• means for enabling hardware to trigger an activation of the dependent power mode of the active-core-dependent collection based on the number of currently-active cores of the multiple cores.

A method by an integrated circuit to implement an active-core-based performance boost, the method comprising:

• receiving an instruction from software to change a power state of the integrated circuit to an independent power mode;
• responsive to receipt of the instruction from the software, activating the independent power mode of the integrated circuit;
• and
• in an absence of an instruction from the software to change the power state of the integrated circuit, conditionally activating a dependent power mode to enter a boosted power state of the integrated circuit, including:
• ascertaining a number of active cores of the integrated circuit;
• comparing the number of active cores to an active core threshold number;
• and
• if the number of active cores comports with the active core threshold number, activating the dependent power mode to cause the integrated circuit to enter the boosted power state.

An integrated circuit comprising:

• multiple cores, each core of the multiple cores configured to be awake if active or asleep if inactive;
• and
• a power mode manager configured to enable activation of a software-accessible power mode collection and a hardware-reserved power mode collection, the software-accessible power mode collection including multiple independent power modes that are configured to be exposed for activation by software executing on the integrated circuit, the hardware-reserved power mode collection including at least one dependent power mode that is configured to be withheld from activation by the software, the power mode manager further configured to:
• ascertain a number of active cores of the multiple cores;
• perform a comparison including the number of active cores and an active core threshold number;
• and
• activate the at least one dependent power mode to cause a boosted voltage or a boosted frequency to be provided to at least one active core of the multiple cores based on the comparison.