Processor Having Concurrent Core And Fabric Exit From A Low Power State
AssigneeIntel Corporation
InventorsAlexander Gendler, Henrietta Bezbroz
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Abstract
In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a plurality of cores, at least some of the plurality of cores having an advanced programmable interrupt controller (APIC) identifier associated therewith;
- a plurality of power management agents associated with the plurality of cores;
- and
- a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving a wake signal and an interrupt destination identifier in a power control unit of a processor while the processor is in a low power state, responsive to receipt of an interrupt in the processor;
- sending the wake signal and the interrupt destination identifier to a plurality of power management agents of the processor via a power management sideband interconnect;
- receiving an indication of a core associated with the interrupt destination identifier;
- and
- concurrently causing the core associated with the interrupt destination identifier and a fabric that couples the plurality of cores to exit the low power state concurrently.
A system comprising:
- a processor having a power controller, a core to execute instructions and a core perimeter logic coupled to the core, the core perimeter logic including a power management agent to access an interrupt destination identifier associated with the core, wherein the power management agent is to send a message to the power controller to request the power controller to cause the core to wake up, responsive to detection of a match between a first interrupt destination identifier of a broadcast message sent to a plurality of cores and the interrupt destination identifier associated with the core;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.