Power control for use of volatile memory as non-volatile memory
AssigneeMicrosoft Technology Licensing, LLC
InventorsBryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
Life of this patent
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Abstract
A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
Claims21
(canceled)
A computing device comprising:
- a volatile memory logically partitioned into a plurality of portions;
- a non-volatile storage device, wherein content of a portion of the plurality of portions is transferable to the non-volatile storage device by a memory transfer operation;
- wherein the computing device is configured to:
- in response to receiving data indicative of a transition from utility to battery power, suspend power to a first core of a processor, wherein power to a first uncore of the processor is maintained at least until the memory transfer operation is completed;
- and
- prevent the processor from receiving interrupt signals while allowing the processor to receive a signal indicative that the memory transfer operation is complete.
A method comprising:
- receiving information indicative of a computing device switching from utility power to battery power;
- initiating, by a first core of a first processor, a memory transfer operation from a page of a volatile memory to a non-volatile memory;
- suspending power to the first core of the first processor;
- maintaining power to a first uncore of the first processor;
- disabling delivery of interrupt signals to the first processor while allowing delivery of the a first signal indicative of completing the memory transfer operation;
- and
- restoring, by the first uncore of the first processor in response to receiving the first signal, power to the first core of the first processor.
A computer-readable storage memory having stored thereon computer-executable instructions that, upon execution by a computer, cause the computer to at least:
- determine, based at least in part on a state of a power source of the computer, to initiate a memory transfer operation from volatile memory to non-volatile memory;
- initiate the memory transfer operation using a first subset of a processor;
- suspend power to the first subset of the processor, wherein power to a second subset of the processor is maintained when power to the first subset is suspended;
- disable delivery of interrupt signals to the processor while allowing delivery of a first signal indicative of completing the memory transfer operation;
- and
- restore power to the first subset of the processor using the second subset of the processor, in response to receiving the first signal.
Dependencies are inferred from the claim text.