Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus

A processor comprising:

• a first semiconductor die including:
• a first core;
• a cache memory;
• a communication bus coupled to the first core, the communication bus to couple the first core and the cache memory;
• a graphics processor;
• a core workload monitor to determine a core workload for the first core;
• a bus workload monitor to determine a bus workload for the communication bus;
• and
• a power control unit including logic to receive the bus workload and to dynamically balance power between the first core and the communication bus based on a power limit for the processor and a comparison between the bus workload and a bus workload threshold, the power limit corresponding to a maximum thermal dissipation capacity for the processor, wherein a power consumption of one of the first core and the communication bus is to be reduced if a thermal value of the processor exceeds the power limit.