Fractional divider using a calibrated digital-to-time converter
AssigneeIntegrated Device Technology, Inc.
InventorsSong Gao, Brian Buell, Katherine T. Blinick
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.
Claims20
An apparatus comprising:
- a first control circuit (i) comprising a plurality of capacitances and (ii) configured to generate an output clock signal in response to a divided clock signal, a first feedback signal and a second feedback signal;
- a second control circuit configured to generate said first feedback signal and an error signal in response to said divided clock signal and a state signal;
- a first feedback circuit configured to generate said state signal in response to said output clock signal;
- and
- a second feedback circuit configured to generate said second feedback signal in response to said error signal, wherein (i) one or more of said capacitances are engaged to add a delay to one or more edges of said output clock signal, (ii) a number of said capacitances engaged is selected to reduce jitter on said output clock signal, and (iii) said capacitances are used each cycle to calibrate said output clock signal.
A method for reducing jitter on a signal, comprising the steps of:
- (A) receiving an input clock signal;
- (B) receiving a configuration signal;
- (C) generating (i) a divided clock signal and (ii) a control signal;
- (D) selecting a number of a plurality of capacitances to engage;
- and
- (E) generating an output clock signal in response to (i) said control signal and (ii) said divided clock signal, wherein (a) a delay is added to one or more edges of said output clock signal by engaging one or more of a plurality of said capacitances, (b) said number of said capacitances engaged is selected to reduce jitter on said output clock signal, and (c) said capacitances are used each cycle to calibrate said output clock signal.
Dependencies are inferred from the claim text.