Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

A computer system for generating a proximity-corrected design layout for photoresist to be used in an etch operation, the system comprising:

• a processor, and
• a memory, the memory storing a look-up table (LUT) and computer-readable instructions for execution on the processor, including instructions for:
• (a) receiving an initial design layout;
• (b) identifying a feature in the initial design layout, the feature's pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate's surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said stack is overlaid with a layer of photoresist pattern corresponding to the design layout;
• (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process;
• (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in the LUT which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF;
• and
• (e) modifying the initial design layout based on at the quantity characteristic of EPE;
• wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.

One or more computer-readable media having a look-up table (LUT) and computer-readable instructions stored thereon, including instructions for:

• (a) receiving an initial design layout;
• (b) identifying a feature in the initial design layout, the feature's pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate's surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said stack is overlaid with a layer of photoresist pattern corresponding to the design layout;
• (c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process;
• (d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in the LUT which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF;
• and
• (e) modifying the initial design layout based on at the quantity characteristic of EPE;
• wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.

A method of estimating a quantity characteristic of an edge placement error (EPE) of an edge of a feature on a semiconductor substrate having a design layout of photoresist overlaid on a material stack, the feature to be etched in a real or simulated plasma-based etch process performed in a correspondingly real or simulated processing chamber under a set of process conditions, the method comprising:

• (a) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) at time t during the etch;
• and
• (b) estimating the quantity characteristic of EPE at time t by comparing the one or more quantities characteristic of the IFPF estimated in (a) to those in a LUT which associates values of EPE at time t with one or more quantities characteristic of the IFPF;
• wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.