Semiconductor device, method for manufacturing same, and display device including same
AssigneeSharp Kabushiki Kaisha
InventorHIROSHI MATSUKIZONO
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AssigneeSharp Kabushiki Kaisha
InventorHIROSHI MATSUKIZONO
Estimating the term…
Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same. A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.
A semiconductor device comprising:
A method for manufacturing a semiconductor device including a semiconductor layer formed of an oxide semiconductor on an insulating substrate, a gate insulating film having tapering side surfaces and formed on the semiconductor layer, a gate electrode having tapering side surfaces and formed on the gate insulating film, a source region and a drain region being low-resistance regions formed in the semiconductor layer on opposite sides with respect to the gate electrode, a silicon nitride film formed on the source region and the drain region of the semiconductor layer, and a source electrode layer and a drain electrode layer respectively in ohmic contact with the source region and the drain region, the method comprising the steps of:
Dependencies are inferred from the claim text.