Implementing prioritized compressed failure defects for efficient scan diagnostics
AssigneeInternational Business Machines Corporation
InventorsSteven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer
Life of this patent
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Abstract
A method and circuits are provided for implementing enhanced scan data testing using an XOR network to prioritize faults to be simulated during diagnostic isolation, and reducing the number of faults requiring re-simulation. A test is run, scan data are applied to scan channels using the XOR network and the output scan data are unloaded. A list of possible faults is identified based on pin flips, and the possible faults to be simulated during diagnostic isolation are prioritized by a number of occurrences in the list, and possible faults are further graded to reduce the number of possible faults requiring re-simulation.
Claims20
A method for implementing enhanced scan data testing a chip using an XOR network comprising:
- applying scan data to scan channels using the XOR network and unloading output scan data to output pins;
- identifying a list of possible faults based on pin flips,
- prioritizing the possible faults to be simulated during diagnostic isolation by a number of occurrences in the list;
- and
- further grading the possible faults to reduce possible faults requiring re-simulation.
A circuit for implementing enhanced scan data testing using an XOR network comprising:
- a first scan channel and a second scan channel;
- and said first scan channel and said second scan channel including a plurality of scannable latches providing input data to logic circuits on a chip and receiving output data from logic circuits on the chip;
- a respective first exclusive or (XOR) for hashing output data from the scannable latches on the first scan channel and the second scan channel, and a respective second exclusive or (XOR) coupled to respective first exclusive or (XOR) on the first scan channel and the second scan channel to hash output data from the respective first exclusive or (XOR);
- a multiple input signature register (MISR) for data collection provided with an associated scan channel;
- and
- a multiplexer coupled to said multiple input signature register (MISR) and between a respective first exclusive or (XOR) and a respective second exclusive or (XOR) on the first scan channel and the second scan channel, and a MISR unload input to a select input of the multiplexer.
A design structure tangibly embodied in a machine readable medium for designing, manufacturing, and testing an integrated circuit, the design structure:
- a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing enhanced scan data testing using an XOR network, said circuit comprising:
- a first scan channel and a second scan channel;
- and said first scan channel and said second scan channel including a plurality of scannable latches providing input data to logic circuits on a chip and receiving output data from logic circuits on the chip;
- a respective first exclusive or (XOR) for hashing output data from the scannable latches on the first scan channel and the second scan channel, and a respective second exclusive or (XOR) coupled to respective first exclusive or (XOR) on the first scan channel and the second scan channel to hash output data from the respective first exclusive or (XOR);
- a multiple input signature register (MISR) for data collection provided with an associated scan channel;
- and
- a multiplexer coupled to said multiple input signature register (MISR) and between a respective first exclusive or (XOR) and a respective second exclusive or (XOR) on the first scan channel and the second scan channel, and a MISR unload input to a select input of the multiplexer, said design structure when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.
Dependencies are inferred from the claim text.