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US 2017/0363676 A1Published application
Design for Test of Stacked Transistors
AssigneePeregrine Semiconductor Corporation
InventorEric S. Shapiro
Life of this patent
Estimating the term…
Abstract
A stack of series coupled transistors comprising, at least two sub-portions of the stack of series coupled transistors, and at least one logic decoder coupled to the at least two sub-portions to turn ON at least one sub-portion.
Claims29
A stack of series coupled transistors comprising:
- at least two sub-portions of said stack of series coupled transistors;
- and
- at least one logic decoder coupled to said at least two sub portions to turn ON at least one sub-portion.
A stack of series coupled transistors comprising:
- at least two sub-portions of said stack of series coupled transistors;
- at least one level shifter coupled to at least one sub-portion of said at least two sub-portions;
- and
- at least one logic decoder coupled to said at least one level shifter to turn ON said at least one sub-portion.
1 more element
A stack of series coupled transistors comprising:
- a first portion of said stack of series coupled transistors;
- a second portion of said stack of series coupled transistors;
- a first level shifter coupled to said first portion;
- a second level shifter coupled to said second portion;
- and
- a logic decoder coupled to said first level shifter and said second level shifter to turn ON at least one of said first portion and said second portion.
3 more elements
A stack of series coupled transistors comprising:
- at least one sub-portion of said stack of series coupled transistors;
- at least one level shifter coupled to said at least one sub-portion;
- and
- at least one logic decoder coupled to said at least one level shifter to turn ON said at least one sub-portion.
1 more element
A stack of series coupled transistors comprising:
- at least one of said stack of series coupled transistors having at least one gate, at least one drain and at least one source;
- at least one blocking capacitor coupled to at least one of said at least one drain and at least one source;
- at least one inverter having at least one inverter output coupled to said at least one gate and at least one inverter input coupled to at least one of said at least one drain and at least one source;
- and
- at least one logic decoder coupled to said at least one inverter to select said at least one inverter.
2 more elements
A method of testing a transistor stack comprising:
- receiving at least one decoder signal;
- setting a state of at least one level shifter based on said at least one decoder signal;
- and
- turning ON at least one portion of said transistor stacked based on the state of the at least one level shifter.
1 more element
A method of testing a transistor stack comprising:
- receiving at least one decoder signal;
- and
- turning ON at least one portion of said transistor stacked based on the received at least one decoder signal.
Dependencies are inferred from the claim text.