Phase-shifter circuit and method of generating a phase-shifted form of a reference timing signal

A method of generating a phase-shifted form of a reference timing signal, the method comprising:

• receiving the reference timing signal;
• receiving a delay control signal;
• and
• delaying transitions within the reference timing signal to generate the phase-shifted form of the reference timing signal, wherein the amount of delay applied to the transitions within the reference timing signal is controllable by the delay control signal;
• wherein the method further comprises:
• receiving at least one re-timed signal comprising transitions re-timed to transitions of the phase-shifted form of the reference timing signal;
• and
• generating the delay control signal for the at least one delay circuit based at least partly on the received at least one re-timed signal.

A radio frequency transceiver comprising a synthesizer arranged to generate at least one timing signal;

• the synthesizer comprising:
• at least one odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer;
• the phase-shifter circuit arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal;
• the phase-shifter circuit comprising:
• at least one delay circuit arranged to receive the reference timing signal and a delay control signal, and to delay transitions within the reference timing signal to generate the at least one phase-shifted form of the reference timing signal, wherein the amount of delay applied by the delay circuit to the transitions within the reference timing signal is controllable by the delay control signal;
• and
• at least one delay control circuit arranged to receive at least one re-timed signal comprising transitions re-timed to transitions of the phase-shifted form of the reference timing signal output by the phase-shifter circuit, and to generate the delay control signal for the at least one delay circuit based at least partly on the received at least one re-timed signal;
• and
• a re-timing circuit arranged to:
• receive the at least one frequency-divided signal;
• receive the 90° phase-shifted form of the reference timing signal;
• and
• re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the at least one timing signal comprising the re-timed transitions of the frequency-divided signal.

The radio frequency transceiver of claim 24, wherein the at least one delay control circuit further comprises:

• a first input filter circuit arranged to receive the first re-timed signal and to generate the voltage signal representative of the first re-timed signal at the first input of the operational amplifier;
• a second input filter circuit arranged to receive the second re-timed signal and to generate the voltage signal representative of the second re-timed signal at the second input of the operational amplifier;
• and
• a capacitance coupled between the output of the operational amplifier and a reference voltage node.