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US 2017/0352404 A1Published application
Refresh control device, and memory device including the same
AssigneeSK hynix Inc.
InventorsJae Seung LEE, Chang Hyun KIM, Yo Sep LEE
Life of this patent
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Abstract
A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
Claims20
A refresh control device comprising:
- a first oscillator configured to generate a first oscillation signal;
- a second oscillator configured to generate a second oscillation signal;
- a counter configured to generate a pre-enable signal synchronized with the first oscillation signal based on a precharge signal;
- and
- a combination circuit configured to output a latch enable signal based on the second oscillation signal and the pre-enable signal.
2 more elements
A refresh control device comprising:
- a first oscillator configured to generate a first oscillation signal;
- a second oscillator configured to generate a second oscillation signal;
- a counter configured to generate a pre-enable signal synchronized with the first oscillation signal based on a precharge signal;
- a binary code generator configured to generate a random binary code signal formed in a random pulse shape based on the second oscillation signal;
- and
- a combination circuit configured to output a latch enable signal based on the random binary code signal and the pre-enable signal.
3 more elements
A refresh control device comprising:
- a first oscillator configured to generate a first oscillation signal;
- a second oscillator configured to generate a second oscillation signal;
- a counter configured to generate a pre-enable signal synchronized with the first oscillation signal based on a precharge signal;
- a binary code generator configured to generate a random binary code signal formed in a random pulse shape based on the second oscillation signal;
- and
- a selection circuit configured to select any one of the random binary code signal and the pre-enable signal based on a selection signal, and output the selected one as a latch enable signal.
3 more elements
A memory device comprising:
- a refresh controller configured to output a latch enable signal synchronized by at least two source signals having different time periods, latch an input row address synchronized with the latch enable signal, and output a smart refresh signal needed to perform a smart refresh operation;
- and
- a bank in which the smart refresh operation is carried out based on the smart refresh signal.
Dependencies are inferred from the claim text.