Hardened White Box Implementation 1
AssigneeGiesecke & Devrient GmbH
InventorsHermann DREXLER, Sven BAUER, Jürgen PULKUS
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Abstract
The invention provides a processor device having an executable, white-box-masked implementation of a cryptographic algorithm implemented thereon. The white-box masking comprises an affine mapping A, which is so designed that every bit in the output values w of the affine mapping A depends on at least one bit of the obfuscation values y, thereby attaining that the output values w of the affine mapping A are statistically balanced.
Claims18
1-16. (canceled)
A processor device having an executable white-box-masked implementation of a cryptographic algorithm implemented thereon, which is configured to generate an output text, from an input text while employing a secret key K, wherein the implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T′ by means of an invertible function f, wherein
- the invertible function f comprises an affine mapping A applied to the computation step S, said mapping being configured to generate output values w from A by applying A to output values s of the computation step S and additionally to one or several obfuscation values y which are statistically independent of the output values s of the computation step S, so that it holds that w=A(S[x], y)=A(s, y);
- and
- the affine mapping A is further so designed that every bit in the output values w of the affine mapping A depends on at least one bit of the obfuscation values y, thereby attaining that the output values w of the affine mapping A are statistically balanced.
Dependencies are inferred from the claim text.