Serializer, and semiconductor apparatus and system including the same
AssigneeSK hynix Inc.
InventorHae Kang JUNG
Life of this patent
Estimating the term…
Abstract
A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.
Claims19
A serializer comprising:
- a first data output circuit configured to receive first data through a first node, provide the first data to an output node in synchronization with a first phase clock and a second phase clock, and precharge a second node in synchronization with a third phase clock;
- and
- a second data output circuit configured to receive second data through the second node, and provide the second data to the output node in synchronization with the second phase clock and the third phase clock.
A serializer comprising:
- a first input buffer configured to receive first data through a first input node, and buffer the first data;
- a first data output circuit configured to provide an output of the first input buffer to an output node in synchronization with a first phase clock and a second phase clock, and precharge a second input node in synchronization with a third phase clock;
- a second input buffer configured to receive second data through the second input node, and buffer the second data;
- and
- a second data output circuit configured to provide an output of the second input buffer to the output node in synchronization with the second phase clock and the third phase clock.
A serializer comprising:
- a first data output circuit configured to receive first data through a first node, and provide the first data to an output node in synchronization with a first phase clock and a second phase clock;
- and
- a second data output circuit configured to receive second data through a second node, and provide the second data to the output node in synchronization with the second phase clock and a third phase clock,
- wherein the first data output circuit performs an emphasis operation for the second data output circuit, in synchronization with the third phase clock.
Dependencies are inferred from the claim text.