Sub-sampling phase-locked loop

A method for controlling an oscillator output signal, the method comprising the steps of

• providing a first delay signal (SDLY1) at a first point (t1) in time and a second delay signal (SDLY2) at a second point in time (t2), wherein the first point in time (t1) is before a first ideal sampling instant for the oscillator output signal (SOUT) and the second point in time (t2) is after a second ideal sampling instant for the oscillator output signal (SOUT),
• providing at least a first sample (S1) of the oscillator output signal (SOUT) at the first point in time (t1) based on the first delay signal (SDLY1) and a second sample (S2) of the oscillator output signal (SOUT) at the second point in time (t2) based on the second delay signal (SDLY2),
• providing a sampler signal (SSAMPL) by interpolating the first sample (S1) and the second sample (S2), and
• controlling the oscillator output signal (SOUT) based on the sampler signal (SSAMPL).

A non-transitory storage medium comprising a computer program that runs on a computer with a program code for performing a method comprising the steps of:

• providing a first delay signal (SDLY1) at a first point (t1) in time and a second delay signal (SDLY2) at a second point in time (t2), wherein the first point in time (t1) is before a first ideal sampling instant for the oscillator output signal (SOUT) and the second point in time (t2) is after a second ideal sampling instant for the oscillator output signal (SOUT),
• providing at least a first sample (S1) of the oscillator output signal (SOUT) at the first point in time (t1) based on the first delay signal (SDLY1) and a second sample (S2) of the oscillator output signal (SOUT) at the second point in time (t2) based on the second delay signal (SDLY2),
• providing a sampler signal (SSAMPL) by interpolating the first sample (S1) and the second sample (S2), and
• controlling the oscillator output signal (SOUT) based on the sampler signal (SSAMPL).