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US 2017/0324410 A1Published application
Clock gating circuit operates at high speed
AssigneeSamsung Electronics Co., Ltd.
InventorsHYUNCHUL HWANG, MINSU KIM
Life of this patent
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Abstract
A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.
Claims19
A clock gating circuit comprising:
- a first precharge circuit configured to charge a first node based on a clock signal;
- a second precharge circuit configured to charge a second node based on the clock signal;
- a first discharge circuit configured to discharge the first node based on the clock signal;
- a second discharge circuit configured to discharge the second node based on the clock signal;
- a first cross-coupled maintain circuit configured to maintain the first node at a charge state according to a control output signal;
- a second cross-coupled maintain circuit configured to maintain the second node at the charge state according to a voltage level of the first node;
- and
- a control circuit configured to control the first discharge circuit to discharge the first node, configured to control the second discharge circuit to discharge the second node, and configured to output the control output signal to the first cross-coupled maintain circuit,
- wherein the clock gating circuit outputs an output clock signal based on a clock enable signal, and
- the output clock signal is either the clock signal or an inverted clock signal.
7 more elements
A clock gating circuit comprising:
- a first transistor having a first end connected to a power supply node and a second end connected to a first node, the first transistor being configured to charge the first node based on a clock signal;
- a second transistor having a first end connected to the power supply node and a second end connected to a second node, the second transistor being configured to charge the second node based on the clock signal;
- a third transistor having a first end connected to the power supply node and a second end connected to the first node, the third transistor being configured to charge the first node based on a voltage level of a third node;
- a fourth transistor having a first end connected to the power supply node and a second end connected to the second node, the fourth transistor being configured to charge the second node based on a voltage level of the first node;
- a fifth transistor configured to discharge the first node based on the voltage level of the third node;
- a sixth transistor having a first end connected to the second node and a second end connected to the third node, the sixth transistor being configured to discharge the second node based on the voltage level of the third node;
- a seventh transistor connected to the fifth transistor;
- and
- a control circuit configured to control the voltage level of the third node based on a clock enable signal,
- wherein when the fifth transistor and the seventh transistor are turned on, the first node is discharged.
7 more elements
A clock gating circuit comprising;
- a first precharge circuit configured to charge a first node based on a clock signal;
- a second precharge circuit configured to charge a second node based on the clock signal;
- a first discharge circuit configured to discharge the first node based on the clock signal;
- a second discharge circuit configured to discharge the second node based on the clock signal;
- a first cross-coupled maintain circuit configured to maintain the first node at a charge state according to control output signal;
- a second cross-coupled maintain circuit configured to maintain the second node at a charge state according to a voltage level of the first node;
- and
- a control circuit configured to control the first discharge circuit to discharge the first node and control the second discharge unit to discharge the second node, based on a clock enable signal, a test enable signal, the voltage level of the first node and an inverted voltage level of the second node, the control circuit being configured to output the control output signal to the first cross-coupled maintain circuit,
- wherein when the clock signal is a first level, the first precharge circuit charges the first node to a second level and the second precharge circuit charges the second node to the second level.
6 more elements
Dependencies are inferred from the claim text.