Multiplexer structure
AssigneeSTMicroelectronics (Rousset) SAS
InventorsAlbert Martinez, Michel Agoyan
Life of this patent
Estimating the term…
Abstract
A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
Claims7
A logic two-to-one multiplexer, comprising:
- two input terminals;
- one output terminal;
- a control terminal;
- and
- four series-connected two-to-one multiplexers, a first multiplexer of said four series-connected two-to-one multiplexers having two inputs connected to the two input terminals, a last multiplexer of said four series-connected two-to-one multiplexers having an output connected to the one output terminal, and the other multiplexers of said four series-connected two-to-one multiplexers having two inputs interconnected to the output of the previous multiplexer in the four series-connected two-to-one multiplexers,
- wherein half of the multiplexers in said four series-connected two-to-one multiplexers are controlled in reverse with respect to another half of the multiplexers in said four series-connected two-to-one multiplexers.
A four-to-one multiplexer, comprising three multiplexers, wherein each multiplexer of the three multiplexers comprises a logic two-to-one multiplexer and each logic two-to-one multiplexer comprises:
- two input terminals;
- one output terminal;
- a control terminal;
- and four series-connected two-to-one multiplexers, a first multiplexer of said four series-connected two-to-one multiplexers having two inputs connected to the two input terminals, a last multiplexer of said four series-connected two-to-one multiplexers having an output connected to the one output terminal, and the other multiplexers of said four series-connected two-to-one multiplexers having two inputs interconnected to the output of the previous multiplexer in the four series-connected two-to-one multiplexers,
- wherein half of the multiplexers in said four series-connected two-to-one multiplexers are controlled in reverse with respect to another half of the multiplexers in said four series-connected two-to-one multiplexers.
A number generation circuit, comprising at least one logic two-to-one multiplexer, said logic two-to-one multiplexer comprising:
- a two input terminals;
- one output terminal;
- a control terminal;
- and
- four series-connected two-to-one multiplexers, a first multiplexer of said four series-connected two-to-one multiplexers having two inputs connected to the two input terminals, a last multiplexer of said four series-connected two-to-one multiplexers having an output connected to the one output terminal, and the other multiplexers of said four series-connected two-to-one multiplexers having two inputs interconnected to the output of the previous multiplexer in the four series-connected two-to-one multiplexers,
- wherein half of the multiplexers in said four series-connected two-to-one multiplexers are controlled in reverse with respect to another half of the multiplexers in said four series-connected two-to-one multiplexers.
Dependencies are inferred from the claim text.