Multiple mode device implementation for programmable logic devices

A computer-implemented method comprising:

• receiving a design identifying operations to be performed by a programmable logic device (PLD);
• and
• synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:
• detecting a logic function operation, a ripple arithmetic operation, and/or an extended logic function operation in the design;
• and
• implementing the detected operation using first and/or second logic cells within a programmable logic block (PLB) of the PLD, each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, wherein:
• the associated mode logic is configured to use a single physical signal output to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode;
• and
• the associated mode logic for at least one of the first and second logic cells is configured to provide the LUT output signal as the logic cell output signal when the selected operational mode for its respective logic cell comprises the logic function operational mode.

A non-transitory machine-readable medium storing a plurality of machine-readable instructions which when executed by one or more processors of a computer system are adapted to cause the computer system to perform a computer-implemented method comprising:

• routing connections to at least first and second logic cells of a programmable logic device (PLD), each logic cell comprising a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT, wherein:
• the associated mode logic is configured to use a single physical output port to provide a logic cell output signal from its respective logic cell corresponding to an operational mode selected from a logic function operational mode, a ripple arithmetic operational mode, and an extended logic function operational mode;
• and
• the associated mode logic for at least one of the first and second logic cells is configured to provide the LUT output signal as the logic cell output signal when the selected operational mode for its respective logic cell comprises the logic function operational mode.