US 2017/0324385 A1 · METHOD, APPARATUS AND SYSTEM FOR BACK GATE BIASING FOR FD-SOI DEVICES

Abstract

At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

Claims20

Dependent claims

A method, comprising:

forming a P-substrate layer over a silicon substrate;
forming a triple-well layer above said P-substrate layer;
forming a first P-well structure for defining a first back gate for a transistor such that said triple-well isolates said first P-well structure from the P-substrate layer;
forming an first oxide layer above said first back gate;
forming a first silicon on oxide (SOI) layer over said first oxide layer;
and
forming a first source region, a first drain region and a first front gate region for forming a transistor comprising said first back gate and said first front gate.

4 more elements

A system, comprising:

a semiconductor device processing system to process a semiconductor wafer for manufacturing a semiconductor device, wherein semiconductor device processing system comprising:
a design unit configured to provide parameter for manufacturing said semiconductor device comprising:
a signal processing unit for processing an input signal to provide an output signal, said signal processing unit comprising:
a first transistor and a second transistor, wherein said first transistor comprises a first back gate electrically coupled to a first front gate;
and
a second transistor operatively coupled to said first transistor, wherein said second transistor, comprises a second back gate electrically coupled to a second front gate;
a gain circuit for providing a gain upon said output signal;
and
a bias circuit to provide a first bias signal to said first back gate and a second bias signal to said second back gate;
and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system for manufacturing said semiconductor device.

8 more elements

Dependencies are inferred from the claim text.

Method, apparatus and system for back gate biasing for fd-soi devices

Life of this patent

Method, apparatus and system for back gate biasing for fd-soi devices

Life of this patent

Abstract

Claims20