Vertical transistor including controlled gate length and a self-aligned junction

A method of forming a gate structure in a vertical transistor, the method comprising:

• forming a semiconductor structure having a first sacrificial layer interposed between proximate and distal doping source layers, the first sacrificial layer surrounding a channel region and defining a desired gate length of the vertical transistor;
• annealing the semiconductor structure such that dopants are diffused from the proximate and distal doping source layers to form opposing proximate and distal S/D extension regions that extend into the channel region;
• selectively removing the first sacrificial layer to form a void that exposes the region;
• filling the void with a gate metal material so as to form a gate structure having a gate length that substantially matches the desired gate length.

A vertical transistor, comprising:

• a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type, the proximate spacer formed on an upper surface of a semiconductor substrate;
• at least one channel region that extends vertically from the proximate doping source layer to the distal doping source layer;
• and
• a proximate S/D extension region adjacent the proximate spacer and a distal S/D extension region adjacent the distal spacer, the proximate and distal S/D extension regions comprising dopants that match the first dopant-type of the proximate and distal doping sources.