Devices and methods for a power transistor having a schottky or schottky-like contact

A method of forming a power transistor structure, comprising:

• providing a substrate wafer;
• forming a drift region on or within the substrate wafer;
• forming a body region on or within the drift region;
• forming an isolation region on subtending from a surface of the substrate wafer;
• forming a gate dielectric on the substrate wafer;
• depositing a gate stack;
• patterning the gate stack;
• forming and patterning a spacer structure on the gate stack;
• patterning and implanting a body contact of a first polarity;
• patterning a source region;
• implanting a dopant segregation implant in the source region;
• low-temperature annealing the dopant segregation implant for providing a Schottky or Schottky-like contact as the source region;
• and
• patterning and defining inter-level dielectric (ILD) and interconnect wiring.

A lateral power transistor structure, comprising:

• a substrate of a first dopant polarity;
• a drift region of a second dopant polarity formed on or within the substrate;
• a body region of a first dopant polarity formed on or within the drift region;
• a gate dielectric film in contact with the substrate;
• a gate structure abutting the gate dielectric film;
• a source region outside the gate structure;
• a drain region formed on the substrate;
• and
• wherein the source region is a Schottky or Schottky-like contact formed substantially near a surface of the substrate for eliminating a parasitic bipolar junction transistor for providing an improved safe operating area, reducing a specific on-state resistance of the lateral power transistor structure, and/or reducing a die size of the lateral power transistor structure.

A vertical trench power transistor structure, comprising:

• a substrate of a first dopant polarity;
• a drift region of a first dopant polarity formed on or within the substrate;
• a body region of a second dopant polarity formed within the drift region;
• a vertical gate structure in the substrate;
• a gate dielectric film on the sidewall of the vertical gate structure;
• a gate structure abutting the gate dielectric film;
• a source region outside the gate structure;
• a drain region formed within or on a top surface or a bottom surface of the substrate;
• and
• wherein the source region is a Schottky or Schottky-like contact formed substantially near a surface of the substrate for eliminating a parasitic bipolar junction transistor for immunity of failures under unclamped inductive switching events.