Back to results
US 2017/0323967 A1Published application
Precise control of vertical transistor gate length
AssigneeInternational Business Machines Corporation
InventorsVeeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
Life of this patent
Estimating the term…
Abstract
Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.
Claims15
A method for forming a transistor, comprising:
- forming a channel fin on a bottom source/drain region;
- forming a dielectric fill around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin;
- forming spacers in the gap;
- etching away the dielectric fill;
- and
- forming a gate stack on sidewalls of the channel fin directly underneath the spacers.
3 more elements
A method for forming a transistor, comprising:
- etching a substrate around a mask to form a first fin and a bottom source/drain region;
- forming a bottom spacer directly on the bottom source/drain region, around the first fin;
- forming a channel fin on the bottom source/drain region;
- laterally etching the first fin to form the channel fin, such that the mask overhangs sidewalls of the channel fin;
- forming a dielectric fill around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin;
- forming spacers having an L-shaped cross-section in the gap, comprising:
- forming a dielectric bilayer film in the gap comprising a bottom film and a top film;
- etching away horizontal regions of the dielectric bilayer film;
- and
- etching away remnant portions of the top film, leaving behind the spacers;
- forming a top source/drain region directly on a top surface of the channel fin, between the spacers;
- etching away the dielectric fill;
- and
- forming a gate stack on sidewalls of the channel fin directly underneath the spacers.
11 more elements
15-20. (canceled)
Dependencies are inferred from the claim text.