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US 2017/0323965 A1Published application
Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator
AssigneeIntel Corporation
InventorsMichael L. HATTENDORF, Pragyansri PATHI, Michael K. HARPER
Life of this patent
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Abstract
Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.
Claims20
A device comprising:
- a pillar disposed over a first region of a substrate, the pillar comprising a semiconductor material;
- an insulator disposed over a second region of the substrate and adjacent to a base portion of the pillar;
- and
- a gate electrode coupled to a fin portion of the pillar in the first region and disposed over the insulator in the second region, wherein the gate electrode has a first depth over the first region and a second depth less than the first depth over the second region, and wherein the insulator has a top surface at a first height above a surface of the substrate over the second region, the fin portion has a bottom surface at the gate electrode coupling to the fin portion at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height.
1 more element
A system comprising:
- a microprocessor comprising:
- a pillar disposed over a first region of a substrate, the pillar comprising a semiconductor material;
- an insulator disposed over a second region of the substrate and adjacent to a base portion of the pillar;
- and
- a gate electrode coupled to a fin portion of the pillar in the first region and disposed over the insulator in the second region, wherein the gate electrode has a first depth over the first region and a second depth less than the first depth over the second region, and wherein the insulator has a top surface at a first height above a surface of the substrate over the second region, the fin portion has a bottom surface at the gate electrode coupling to the fin portion at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height;
- a display screen communicatively coupled to the microprocessor;
- and
- a wireless transceiver communicatively coupled to the microprocessor.
5 more elements
A microprocessor comprising:
- an SRAM memory device including a transistor comprising:
- a pillar disposed over a first region of a substrate, the pillar comprising a semiconductor material;
- an insulator disposed over a second region of the substrate and adjacent to a base portion of the pillar;
- and
- a gate electrode coupled to a fin portion of the pillar in the first region and disposed over the insulator in the second region, wherein the gate electrode has a first depth over the first region and a second depth less than the first depth over the second region, and wherein the insulator has a top surface at a first height above a surface of the substrate over the second region, the fin portion has a bottom surface at the gate electrode coupling to the fin portion at a second height above the surface of the substrate and a top surface at a third height above the surface of the substrate, and the first height is between the second height and the third height.
2 more elements
Dependencies are inferred from the claim text.