Back to results
US 2017/0323952 A1Published application
Integrated strained stacked nanosheet FET
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Ramachandra Divakaruni, Juntao LI, Xin Miao
Life of this patent
Estimating the term…
Abstract
Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.
Claims20
A transistor, comprising:
- a plurality of stress liners;
- one or more channel structures, suspended at opposite ends from the plurality of stress liners, wherein the stress liners provide a stress on the one or more channel structures;
- a gate formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate;
- and
- a source and drain region formed on opposite sides of the gate.
2 more elements
A transistor, comprising:
- a plurality of stress liners;
- one or more channel structures, suspended at opposite ends from the plurality of stress liners, wherein the stress liners provide a stress on the one or more channel structures;
- a plurality of gate stacks formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate;
- a dielectric liner formed directly on the plurality of gates;
- and
- a source and drain region formed on opposite sides of the plurality of gates, outside of the dielectric liner.
3 more elements
A transistor, comprising:
- a plurality of silicon nitride stress liners;
- one or more channel structures, suspended at opposite ends from the plurality of stress liners, wherein the stress liners provide a stress on the one or more channel structures;
- a plurality of gates stacks formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate;
- a dielectric liner formed directly on the plurality of gates;
- and
- a source and drain region formed on opposite sides of the plurality of gates, outside of the dielectric liner.
3 more elements
Dependencies are inferred from the claim text.