US 2017/0323946 A1Published application

Group iii-n transistor on nanoscale template structures

AssigneeIntel Corporation

InventorsHan Wui THEN, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Benjamin CHU-KUNG, Sanaz GARDNER, Seung Hoon SUNG, Robert S. Chau

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Claims20

Dependent claims

A semiconductor device, comprising:

a first channel material stack above a substrate, the first channel material stack comprising an uppermost surface, a lowermost surface, and sidewalls surfaces, and the first channel material stack comprising a Group III-N channel layer between and laterally adjacent to an outer polarization layer and an inner transition layer;
a second channel material stack above the substrate, the second channel material stack comprising an uppermost surface, a lowermost surface, and sidewalls surfaces, and the second channel material stack comprising a Group III-N channel layer between and laterally adjacent to an outer polarization layer and an inner transition layer, wherein the inner transition layer of the second channel material stack faces the inner transition layer of the first channel material stack;
a gate dielectric layer on the uppermost surface, the lowermost surface, and the sidewalls surfaces of both of the first and second channel material stacks;
a gate electrode layer on the gate dielectric layer and completely surrounding the first and second channel material stacks;
and
source and drain regions on either side of the gate stack and coupled to the first and second channel material stacks.

3 more elements

A method of fabricating a semiconductor device, the method comprising:

forming a first channel material stack above a substrate, the first channel material stack comprising an uppermost surface, a lowermost surface, and sidewalls surfaces, and the first channel material stack comprising a Group III-N channel layer between and laterally adjacent to an outer polarization layer and an inner transition layer;
forming a second channel material stack above the substrate, the second channel material stack comprising an uppermost surface, a lowermost surface, and sidewalls surfaces, and the second channel material stack comprising a Group III-N channel layer between and laterally adjacent to an outer polarization layer and an inner transition layer, wherein the inner transition layer of the second channel material stack faces the inner transition layer of the first channel material stack;
forming a gate dielectric layer on the uppermost surface, the lowermost surface, and the sidewalls surfaces of both of the first and second channel material stacks;
forming a gate electrode layer on the gate dielectric layer and completely surrounding the first and second channel material stacks;
and
forming source and drain regions on either side of the gate stack and coupled to the first and second channel material stacks.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/656,480Filed 21 Jul 2017
Priority: 19 Dec 2012
Published: 9 Nov 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 62/8503
Being Group III-V materials, e.g. GaAs: nitride Group III-V materials, e.g. AlN or GaN
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/4755
Having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs: having wide bandgap…

Family

Application13/720,852Division · filed 19 Dec 2012
Application14/303,513Continuation · filed 12 Jun 2014
Application14/581,722Continuation · filed 23 Dec 2014
Application14/937,819Continuation · filed 10 Nov 2015
Application15/135,441Continuation · filed 21 Apr 2016
Application15/656,480Continuation
Application14/303,513Division
US 10,096,683 B2Related patent
US 2014/0170998 A1Published application
US 2014/0291693 A1Published application
US 2015/0108496 A1Published application
US 2016/0064491 A1Published application
US 2016/0240617 A1Published application
US 8,768,271 B1Related patent
US 8,954,021 B2Related patent
US 9,219,079 B2Related patent
US 9,362,369 B2Related patent
US 9,716,149 B2Related patent
US 2017/0323946 A1This patent

From the US filing history. Foreign family members aren’t listed.