Finfet device structure and method for forming same
AssigneeSilicon Space Technology Corporation, d.b.a. Vorago Technologies, Inc.
InventorSTEVEN HOWARD VOLDMAN
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Abstract
A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.
Claims34
A FinFET device comprising:
- a semiconductor body having a first conductivity type and having an upper surface;
- a fin body disposed on the upper surface of the semiconductor body;
- an isolation structure disposed in the semiconductor body below the upper surface and having respective first and second regions disposed on opposite sides of the fin body;
- a fin connecting region disposed in the semiconductor body below the fin body and between the first and second isolation regions;
- a gate dielectric layer disposed on three sides of the fin body;
- a gate electrode disposed on the gate dielectric layer;
- and
- a heavily-doped buried layer of the first conductivity type disposed in the semiconductor body, extending laterally beneath the fin connecting region and beneath the first and second isolation regions, and having a higher doping density than the semiconductor body.
A FinFET device comprising:
- a semiconductor body having a first conductivity type and having an upper surface;
- a fin body disposed on the upper surface of the semiconductor body;
- an isolation structure disposed in the semiconductor body below the upper surface and having respective first and second regions disposed on opposite sides of the fin body;
- a fin connecting region disposed in the semiconductor body below the fin body and between the first and second isolation regions;
- a gate dielectric layer disposed on three sides of the fin body;
- a gate electrode disposed on the gate dielectric layer;
- a buried oxide (BOX) layer disposed in the semiconductor body and extending laterally beneath the fin connecting region and beneath the first and second isolation regions;
- a vertical conductive region disposed in the semiconductor body between a surface contact and the BOX layer, and providing a lower resistance than otherwise would be provided by the semiconductor body in the absence of the vertical conductive region;
- and
- a substrate contact pillar extending from the semiconductor surface, through the BOX layer, and to the semiconductor body below the BOX layer, said substrate contact pillar being laterally disposed within the vertical conductive region to thereby form an integrated vertical contact structure.
Dependencies are inferred from the claim text.