Block Layer in the Metal Gate of MOS Devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
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Abstract
A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
Claims20
An integrated circuit device comprising:
- a semiconductor substrate;
- an Inter-Layer Dielectric (ILD) over the semiconductor substrate;
- gate spacers in the ILD;
- and
- a replacement gate in the ILD and between opposite portions of the gate spacers, wherein the replacement gate comprises:
- a gate dielectric layer;
- a titanium aluminum layer over the gate dielectric layer;
- a cobalt tungsten layer over the titanium aluminum layer;
- and
- a cobalt layer over the cobalt tungsten layer.
An integrated circuit device comprising:
- a substrate;
- a gate stack disposed over the substrate, the gate stack comprising:
- a gate dielectric layer;
- a metal layer disposed over the gate dielectric layer, the metal layer having an n-work function;
- a block layer disposed over the metal layer;
- and
- a wetting layer disposed over the block layer;
- a gate spacer adjacent to the gate stack;
- and
- an Inter-Layer Dielectric (ILD) over the substrate and adjacent to the gate stack.
An integrated circuit device comprising:
- a wetting layer over a semiconductor substrate, the wetting layer comprising a first horizontal portion and a first vertical portion;
- a block layer, the block layer comprising a second horizontal portion and a second vertical portion, the second vertical portion laterally adjacent to an outer surface of the first vertical portion;
- a metal layer, the metal layer comprising a third horizontal portion and a third vertical portion, the third vertical portion laterally adjacent to an outer surface of the second vertical portion;
- a sidewall spacer laterally adjacent to the third vertical portion;
- and
- a gate dielectric layer over the semiconductor substrate, the gate dielectric layer interposed between the first horizontal portion and the semiconductor substrate.
Dependencies are inferred from the claim text.