Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
AssigneeInternational Business Machines Corporation
InventorsArvind Kumar, Mark Lamorey
Life of this patent
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Abstract
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.
Claims20
A method for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, the method comprising:
- selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer;
- manufacturing the second wafer in accordance with the selected periodicity;
- placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer;
- stacking the first wafer onto the second wafer using a bonding material;
- and
- forming a Through-Silicon via connecting a portion of the first wafer to a portion of the second wafer.
11-12. (canceled)
A non-transitory computer readable storage medium comprising a computer readable program for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
- selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer;
- manufacturing the second wafer in accordance with the selected periodicity;
- placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer;
- and
- stacking the first wafer onto the second wafer using a bonding material,
- wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.
A method for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer, the method comprising:
- selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer;
- manufacturing the second wafer in accordance with the selected periodicity;
- placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer;
- and
- stacking the first wafer onto the second wafer using a bonding material,
- wherein the first wafer comprises logic circuitry, and the second wafer comprises a backside illuminated image sensor.
Dependencies are inferred from the claim text.