Thin film transistor array panel and manufacturing method thereof

A method for manufacturing a thin film transistor array panel, the method comprising:

• forming a buffer layer by depositing a first insulating material on a substrate;
• forming a semiconductor layer by depositing and patterning an oxide semiconductor material on the buffer layer;
• forming a gate insulating layer by depositing a second insulating material on the substrate;
• forming a gate conductive layer by depositing a conductive material on the gate insulating layer;
• forming a photosensitive film pattern on the gate conductive layer by coating the gate conductive layer with a photoresist and patterning the photoresist through an exposure process using a mask;
• etching the gate conductive layer by using the photosensitive film pattern as a mask to form a gate electrode;
• etching the gate insulating layer by using the photosensitive film pattern as a mask to form a gate insulator;
• and
• etching the buffer layer by using the semiconductor layer as a mask.

A thin film transistor array panel comprising:

• a substrate;
• a thin film transistor disposed on the substrate and including a first layer, wherein the first layer includes a semiconductor, a source electrode, and a drain electrode, wherein the semiconductor is between the source electrode and the drain electrode;
• and
• a buffer layer disposed between the first layer and the substrate and including an inorganic insulating material,
• wherein a surface area of a bottom surface of the first layer is greater than or equal to a surface area of a top surface of the buffer layer.