Vertical memory devices
OwnerKohji KANAMORI, Min-Yeong Song +1inventors
InventorsKohji KANAMORI, Min-Yeong Song, Shin-Hwan Kang
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Abstract
A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.
Claims20
A vertical memory device, comprising:
- a lower circuit pattern on a substrate;
- a plurality of gate electrodes on the lower circuit pattern, the plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate;
- a channel extending through the gate electrodes in the first direction;
- a memory cell block including a first common source line (CSL), the first CSL extending in a second direction substantially parallel to the upper surface of the substrate;
- and
- a first contact plug connected to the lower circuit pattern and the first CSL, the first contact plug overlapping the first CSL in the first direction.
A vertical memory device, comprising:
- a lower circuit pattern on a substrate;
- a plurality of gate electrodes on the lower circuit pattern, the plurality of gate electrodes being spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate;
- a channel extending through the gate electrodes in the first direction;
- a memory cell block including a plurality of conductive patterns extending in a second direction substantially parallel to the upper surface of the substrate, at least one of the conductive patterns extending at least a portion of the gate electrodes;
- and
- a first contact plug connected to the lower circuit pattern, the first contact plug being under the plurality of conductive patterns.
A semiconductor device comprising:
- a substrate;
- a first active region on the substrate;
- a plurality of first impurity regions in the first active region;
- a first insulating layer on the first active region;
- a base layer on the first insulating layer;
- a plurality of second impurity regions in the base layer;
- a plurality of circuits on top of the base layer;
- a conductive region in the plurality of circuits;
- and
- a contact plug connected to the conductive region and to the first active region, the contact plug under the conductive region.
Dependencies are inferred from the claim text.